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Objective ICT-2007.3.1: Next-Generation Nanoelectronics Components and Electronics
Integration
Target outcome:
The objectives are to advance miniaturisation in baseline CMOS technology targeting digital components and complex digital Systems on Chip ("More Moore"); to master diversification targeting non-digital applications, heterogeneous integration in Systems-on-Chip or Systemsin- a-Package ("More than Moore") and to prepare for the technology generation beyond the CMOS scaling limits ("beyond CMOS").
a) “More Moore” targets nanoelectronics devices beyond 32 nm following the International Technology Roadmap for Semiconductors (ITRS). Specific issues are the increasing process variability and expected physical and reliability limitations of devices and interconnects as well as the need for new circuit architectures and characterisation methods and techniques.
"More than Moore" targets heterogeneous System-on-Chip (SoC) i.e. cost efficient integration of computing, processing and storage with other system functions of various scaling factors (such as analogue, RF [from extremely low frequency up to millimetrewave and beyond], high speed, high power, high voltage, and interface technologies) on a single chip. It also targets System-in-Package (SiP) i.e. integration of different types of chips and devices in a single package or compact subsystem. Specific issues are power consumption, electro-magnetic interference and heat dissipation.
Industrially-driven projects will target:
1. Advances in Integration and Miniaturisation Technologies, and in Devices covering nanoelectronics process technology, metrology, materials, basic device and interconnect structures and related concepts and tools for modelling and simulation for below 32 nm CMOS and for System-on-Chip. Changes in the electrical characteristics, in thermal and mechanical behaviour, in performance, reliability, testability, manufacturability and power consumption of the components need to be addressed. Integration technology also includes wafer level packaging, assembly technology, integration of passives and 3D packaging.
2. Design technologies for next-generation components and electronics integration. They must support a chip complexity of billions of transistors and take into account the increased process variability and changing performances of the advanced devices and processes. This requires a step increase in design productivity for instance through standardised Intellectual Property reuse and scalable and programmable chip architectures. Also targeted are design platforms for SoC and SiP supporting a heterogeneous, global and comprehensive performance simulation of different technologies covering multiple aspects including electrical, optical, mechanical and thermal behaviour. Emphasis will be put on SoC and SiP system design solutions from formal application specification down to physical implementation, and on the effectiveness of co-simulation between different description levels.
3. Manufacturing technologies for: reliable, cost effective industrial manufacturing of sub-45 nm chips; SoC and SiP processes; flexible, automated, adaptive, on-demand and short cycle time manufacturing under economically favourable conditions. This will be based on: (i) models, tools and equipment for AEC/APC-based18 manufacturing and maintenance; supporting metrology, characterisation and information tools and methods; (ii) advanced modelling techniques and chip design for increasing manufacturability, production yield, testability and reliability and linking manufacturing with design; (iii) alternative pattern transfer technologies, such as maskless lithography; (iv) characterisation techniques supporting multi-site and single wafer, small batch manufacturing; (v) handling of thin wafers and assembly of single chips. This also includes preparatory activities for 450-mm wafer processing and joint assessment of manufacturing and metrology equipment for chips and SiPs by equipment suppliers and users.
b) “Beyond CMOS” targets advanced technologies and functional devices beyond the traditional ITRS shrink path. It involves new non-FET based logic and memory, and its possible integration with CMOS. A matching of integration, manufacturability and system capability requirements shall be demonstrated in industry-guided pilot projects.
c) Support measures will complement the research activities:
- Access to prototyping, design expertise and training for SMEs.
18 AEC/APC Advanced Equipment and Process Control
- Access for universities and research institutes to affordable industrial design tools, state-of-the-art technologies for prototyping and training.
- Roadmapping, benchmarking and definition of selection criteria for the industrial use of “Beyond CMOS” technologies.
- Stimulating the interest of young people in pursuing a multidisciplinary career encompassing electronics.
- Supporting the development of RTD strategies through roadmapping, consensus building, coordination with Member or Associated States, and international cooperation.
- CSA aiming at coordinating related national, regional and EU-wide RTD programmes or activities.
Expected impact:
• Strengthened competitiveness of European nanoelectronics supply industry across a complete value-chain involving large, mid-sized and small companies, enabling European industry to lead and anticipate progress in the context of the ITRS roadmap.
• New electronics applications of high economic and socio-economic relevance in e.g. communications, health, environment, transport and security.
• European research organisations in leading positions with an increased number of highskilled jobs in design and user industries and related services.
Funding schemes
a-b): CP, NoE; c): CSA
Call FP7-ICT-2007-